View STLC4420A_277692.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

STLC4420A
Single chip 802.11b/g/a WLAN radio
Feature summary

Extremely small footprint Low power consumption High performance dual band solution,operating at 2.4 GHz and at 5 GHz Fully compliant with the IEEE 802.11b ,802.11g and 802.11a WLAN standards Support for 54, 48, 36, 24, 18, 12, 9, and 6Mbps OFDM, 11 and 5.5Mbps CCK and legacy 2 and 1Mbps data rates at 2.4 GHz Support for 54, 48, 36, 24, 18, 12, 9, and 6Mbps OFDM at 5 GHz Single chip 802.11b/g/a WLAN solution with fully integrated: - Zero IF (ZIF) transceiver, - Voltage controlled oscillator (VCO), - High-speed A/ D and D/A converters, - Radio power management unit (PMU), - OFDM and CCK baseband processor, - ARM9 media access controller (MAC), - SPI serial host interface (up to 48Mbps) - PA bias control - Flexible integrated power management unit - Glueless FEM interface Intelligent power control, including 802.11 power save mode Fully integrated Bluetooth coexistence Mode selectable SPI or SDIO host interface (up to 48Mbps)
LFBGA228 (12.5x7x1.4mm)

Computer peripherals Cable replacement
Description
The STLC4420A is a single chip dual band WLAN solution for embedded, low-power, high performance and very small form factor mobile applications. The product conforms to the IEEE 802.11b, 802.11g and 802.11a protocols operating in the 2.4 GHz and 5 GHz frequency band, supporting OFDM data rates of 54, 48, 36, 24, 18, 12, 9, and 6Mbps in the both bands and CCK data rates of 11 and 5.5Mbps and legacy data rates of 2 and 1Mbps at 2.4 GHz. The STLC4420A is a fully integrated wireless radio including a ZIF transceiver, RF synthesizer/VCO, high-speed data converters, an OFDM/CCK digital baseband processor, an ARM9-based MAC and a complete power management unit with integrated PA bias control. An external dual band FEM completes a highly integrated chip set solution. Host control is provided by a flexible serial interface (SPI or SDIO) supporting bit rates of 48Mbps. For maximum flexibility, the STLC4420A accepts system reference clock frequencies of 19.2, 26, 38.4 and 40 MHz. A reference design evaluation platform of hardware and software is provided to system integrators to rapidly enable wireless connectivity to mobile platforms..
Applications

Cellular phones Personal digital assistants (PDA) Portable computers Hand-held data transfer devices Cameras
Order codes
Part number STLC4420A April 2006 Op. Temp. range, C -30 to 85 Rev 1 Package LFBGA228 1/40
1
Contents
STLC4420A
Contents
1 2 Block diagram and application circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 Pin descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
2.1 Signal description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
3 4
Electrical specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Serial host interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
4.1 4.2 4.3 4.4 4.5 4.6 4.7 4.8 4.9 Host pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 SPI mode selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 AHB masters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 Host registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 Host writes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 Host multi-word writes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 Host reads . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 Host multi-word reads . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 ARM AHB slave access . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
5
Registers description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
5.1 5.2 5.3 5.4 5.5 5.6 5.7 5.8 5.9 5.10 5.11 5.12 5.13 ARM interrupt register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 ARM interrupt acknowledge . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 ARM interrupt enable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 Host interrupt register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 Host interrupt enable register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 Host interrupt acknowledge register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 General purpose 1 and 2 communication registers . . . . . . . . . . . . . . . . . 33 Device control/status register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 DMA data register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 DMA write control register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 DMA write length register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 DMA write base address register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 DMA read control register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
2/40
STLC4420A
Contents
5.14 5.15
DMA read length register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 DMA read base address register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
6
Package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
3/40
1
4/40
2.8V 1.8V 1.8V 1.2V 1.8V 3.6V 6 VBATT GROUND
1M
Figure 1.
Antenna Dual Band
PMU_RSET PMU_CREF
Power Management Unit (PMU)
Diplexer
VCO_CAP VDD_VCO
4.64k 68nF
1uF
1.0uF
BPF
VCO_LOOP LB_LNA_IN+ LB_LNA_INLB_TX_OUT
Block diagram and application circuit
220pF
RF ZIF Section RF VCO Rx Downconverter Tx Upconverter Baseband Filters Baseband Processor (BBP) Media Access Controller (MAC) ARM9 WEP
Balun
Host CPU
FEM
HB_LNA_IN+ HB_LNA_INHB_TX_OUT
inc PA Switches OFDM/CCK Modulation
PA_DET HB_PA_BIAS LB_PA_BIAS PA_RREF
Balun
SPI_CSX SPI_CLK SPI_DIN SPI_DOUT HOST_IRQ VIO POWER_UP SLEEP_CLK OSC_EN REF_CLK
Bluetooth Device
TX_CONF RF_ACTIVE STATUS FREQ
High Speed Data Converters
Block diagram and application circuit
20k
HB_LNA_EN SW1 SW2 SW3
Switch Control STLC4420
STLC4420A block diagram and application circuit (standard front end module)
STLC4420A
Note: Refer to evaluation platform schematics for optimized component values.
STLC4420A
Pin descriptions
2
Figure 2.
Pin descriptions
STLC4420A pin connections
N PA_ RREF 1 PA_ PA_ RSRV_ BIAS24 BIAS24 NC 2 VDD_ BIAS 3 HISPEED RSRV_ RSRV_ _BUS_SEL NC NC 4 RSRV_ AGND MODE0 NC 5 AGND 6 VDDA 7 AGND 8 VDDD DGND AGND 9 REF_ CLK 10 AGND FB_V2 AGND 11 VDDA V2OUT AGND 12 VDDA_ OSC_EN PLL VDDD 13 RSRV_ RSRV_ RSRV_ RSRV_ RSRV_ NC FB_V2X V2XOUT SW2 NC NC NC NC DGND VDDD VBATV2 VBATV4 DGND 14 V1OUT 15 VBAT V1 16 LB_ VPA 17 SER_ VDDD MODE 18 RSRV_ VDD_ RSRV_ NC CORE NC 19 TMS 20 VDD_ CORE 21 TRSTN GP1_3 GPIO7 22 RSRV_ GPIO6 GPIO1 GP1_7 NC 23 RSRV_ STAND DGND BY2 GPIO3 GND 24 N M L K J H G F E D C B A EMU_ POWER_ UP VDIG CREF IRES EMU_ RSRV_ DGND SCL NC VDD_ LF_ GP1_4 XTAL_IN CORE 23 DGND DGND 24 TDI VDDD GP2_13 GPIO8 DGND DGND VI2C DGND SPI_CLK GP2_8 22 VDDD RSRV_ NC FREQ VDD_ UART_ CORE SIN 21 STAND TCLK BY1 UART_ SOUT VIO SPI_CSX 20 DGND DGND DGND VDD_ CORE TX_ CONF STATUS 19 POR_ V2I GP2_9 HOST_ GPIO4 IRQ 18 VDD_ CORE POR_ V2O SPI_ GP2_10 DOUT DGND 17 EMU_ VDD_ RSRV_ RSRV_ GNDA_ RSRV_ PLL VDDD DGND CORE V4OUT DGND NC GP2_12 NC NC VBAT V2X SW4 16 HB_ VPA DGND DGND DGND DGND EMU_ GND DGND VDDD GPIO5 VBAT VDDD SW3 15 14 AGND VCC_ LNA SW1 13 AGND PA_ DET0 PA_ DET1 12 AGND AGND AGND AGND AGND VDDA 11 RSRV_ NC AGND AGND AGND AGND Q_ Q_ AGND TEST- TEST+ 10 AGND AGND AGND I_ I_ AGND TEST- TEST+ 9 RSRV_ NC AGND AGND AGND AGND AGND AGND VDDA 8 POR_ RSRV_ NC V4O AGND AGND AGND AGND AGND VCO_ CAP 7 POR_ V4I MODE1 AGND AGND AGND AGND AGND VDD_ VCO 6 AGND AGND VCO_ LOOP 5 AGND AGND VDD_ QLO 4 AGND PA_ VDDS_ BIAS5 PRESR AGND TX_ GND TX_ GND LNA_ AGND AGND AGND SHIELD AGND VDDA 3 TX_ GND TX_ GND VDDA TX_ LNA_ LNA_ LNA_ LNA_ GND SHIELD SHIELD SHIELD SHIELD AGND VDDA 2 M L K J H G F E D C B A VDDA 1 PA_ RSRV_ VDDA_ HB_TX_ LB_TX_ TX_ HB_ HB_ LB_ LB_ RREF OUT GND LNA_IN- LNA_IN+ LNA_IN- LNA_IN+ AGND NC SYNTH OUT
V4_OUT RF_ EMU_ TDO SEL DAT2 ACTIVE SPI_DIN SDA
5/40
Pin descriptions
STLC4420A
2.1
Table 1.
Pin name
Signal description
STLC4420A signal descriptions
Pin number Type Internal resistor Function
RF front end interface pins LB_LNA_INLB_LNA_IN+ HB_LNA_INHB_LNA_IN+ LNA_SHIELD LB_TX_OUT HB_TX_OUT SW1 SW2 SW3 SW4 PA_BIAS24 D1 C1 F1 E1 C2, C3,D2, E2, F2 H1 J1 A13 A14 A15 A16 N2, M2 RF input RF input RF input RF input RF shield RF output RF output digital output digital output digital output digital output analog output 100 RF Differential 100 RF Differential Power amplifier bias control (2.4 GHz). DAC full-scale output current determined by PA_RREF resistor. Power amplifier bias control (5 GHz). DAC full-scale output current determined by PA_RREF resistor. Analog reference resistor. A 20K ohm typical resistor sets the PA_BIAS full-scale output current. PA Detector Input 0. (2.4 GHz) PA Detector Input 1. (5 GHz) Complementary transmit/receive antennaswitch control outputs. I/O level determined by VDDA supply input. Low band (2.4 GHz) 100 RF differential RX inputs. High band (5 GHz) 100 RF differential RX inputs. Low noise amplifier (LNA) input shield pins. 50 RF transmit (TX) low band (2.4 GHz) single ended output. 50 RF transmit (TX) low band (5 GHz) single ended output.
PA_BIAS5
L3
analog output
-
PA_RREF PA_DET0 PA_DET1
N1, M1 B12 A12
analog reference analog input analog input
-
Resistor ladder
Host interface and clock pins DAT2 F24 1.8 V (VIO) digital I/O 1.8 V digital output, VIO domain 1.8 V digital input 1.8 V digital output 1M Pull-Down No Pull SDIO data I/O bit 2. Not used in SPI mode. Host interrupt request. Typically asserted to request a SPI data transfer. In SDIO mode pin = DAT1. Power up enable from host Oscillator enable output. Initially driven high upon powerup, under firmware control after initialization.
HOST_IRQ
A18
POWER_UP
H23
OSC_EN
N13
6/40
STLC4420A Table 1.
Pin name
Pin descriptions STLC4420A signal descriptions (continued)
Pin number Type Internal resistor Function Reference clock input (19.2, 26.0, 38.4 or 40.0 MHz). Use a 1000pF typical series blocking capacitor. 32KHz typical sleep clock input from host. SPI clock from host SPI chip select from host SPI data input for 4-wire modes. In 3-wire modes, this is the data input/output signal. SPI data output for 4-wire modes only. In SDIO mode pin = DAT0. No Pull Firmware controlled GPIO typically implementing Bluetooth coexistence FREQ input function. Assigned to ARM MAC GP2-6. Firmware controlled GPIO typically implementing Bluetooth coexistence RF_ACTIVE input function. Assigned to ARM MAC GP2-5. Firmware controlled GPIO typically implementing Bluetooth coexistence STATUS input function. Assigned to ARM MAC GP2-4. Firmware controlled GPIO typically implementing Bluetooth coexistence TX_CONF output function. Assigned to ARM MAC GP2-3. MODE strapping pins are pimarily used to properly initialize the PLL for following REF_CLK frequencies. Connect appropriate pin to ground plane for a logic 0 input or to 1.8V power plane (through a 4kohm resistor) for a logic 1. MODE(1:0) = 00 => 19.2 MHz MODE(1:0) = 01 => 40 MHz default, no pull needed MODE(1:0) = 10 => 26 MHz MODE(1:0) = 11 => 38.4 MHz (Note: M5=RX0, L6=RX1) High speed internal bus selection input. Needs to be pulled down through 2.5K ohm to set the proper high speed bus mode. (Note: N4 = ANTSELTST+)
REF_CLK
N10
Clock input 1.8 V (VIO) digital input 1.8 V (VIO) digital input 1.8V (VIO) digital input 1.8 V (VIO) digital I/O 1.8 V (VIO) digital output 1.8 V (VIO) GPIO (input)
LF_XTAL_IN SPI_CLK SPI_CSX SPI_DIN SPI_DOUT
B23 B22 A20 D24 B17
FREQ
C21
RF_ACTIVE
E24
1.8 V (VIO) GPIO (input)
No Pull
STATUS
A19
1.8 V (VIO) GPIO (input)
No Pull
TX_CONF
B19
1.8 V (VIO) GPIO (output) 1.8 V digital input
No Pull
MODE0
M5
MODE1
L6
1.8 V digital input
HISPEED_ BUS_SEL
N4
1.8 V digital input
7/40
Pin descriptions Table 1.
Pin name
STLC4420A
STLC4420A signal descriptions (continued)
Pin number Type Internal resistor Function
Power supply pins POR_V2O L17 1.8V (V2) Digital Input 1.8V (V2) Digital Output 2.8V (V4) Digital Input 2.8V (V4) Digital Output BB/MAC Power on Reset Input EMU Power on Reset Output. A more detailed description could be added from the ST EMU spec Transceiver Power on Reset Input EMU Power on Reset Output. A more detailed description could be added from the ST EMU spec Battery supply inputs for regulator V2X of the EMU. Decouple . Decouple to a solid ground plane using a ceramic capacitor located as close a possible to the VBAT pins. Battery supply inputs for regulator V2 of the EMU. Decouple to a solid ground plane using a ceramic capacitor located as close a possible to the VBAT pins. Battery supply input for regulator V1 of the EMU. Decouple to a solid ground plane using a ceramic capacitor located as close a possible to the VBAT pins. Battery supply input for regulator V4 of the EMU. Decouple to a solid ground plane using a ceramic capacitor located as close a possible to the VBAT pins. Indicates power regulator standby status with STANDBY_1. A more detailed description should be taken from the ST EMU specification Indicates power regulator standby status with STANDBY_1. A more detailed description should be taken from the ST EMU specification Selects Serial Host Interface Mode. Set to Logic High for SPI mode, set to Logic Low for SDIO mode Battery supply inputs. Decouple to a solid ground plane using a ceramic capacitor located as close a possible to the VBAT pins. Supply pin for SW1 to SW4 digital output drivers. (3.6V Nominal)
POR_V2I
L18
POR_V4I
M6
POR_V4O
M7
VBATV2X
B16
VBATV2
N24 Supply Input (3.6V)
VBATV1
N16
VBATV4
M14
STANDBY1
M20
1.8 Digital Output
STANDBY2
M24
1.8 Digital Output
SER_MODE
M18
1.8V (VIO) Digital Input Supply Input (3.6V) Supply Input (3.3V)
VBAT
C15
VDIG
G23
-
8/40
STLC4420A Table 1.
Pin name
Pin descriptions STLC4420A signal descriptions (continued)
Pin number Type Internal resistor Function Digital 1.8V I/O power supply input pin dedicated to the EMU I2C bus interface. Connect to ground if the I2C interface of the EMU is not connected (EMU_SCL, EMU_SDA) Host digital I/O supply input for SPI and Bluetooth interfaces. Linear regulator 1.8V output. Linear regulator 1.8V output. Linear regulator 1.2V output. Linear regulator output selectable for 2.81V or 3.11V. Output voltage controlled by V4_OUTSEL pin G24. Control input for selection of V4OUT regulator output voltage. Logic 0 = 0=2.81V, 1= 3.11V Sense line for V2 regulator. Connect to V2OUT pin M12 with a short trace. Sense line for V2X regulator. Connect to V2XOUT pin B14 with a short trace. Reference capacitor for internal Power Management Unit (PMU). Connect a 1uF capacitor to a solid board gound plane. Reference resistor for the internal Power Management Unit (EMU). Connect a 1M resistor to a solid board ground plane. Analog 1.8V supply input pins. Decouple to a solid ground plane using ceramic capacitors located as close a possible to the appropriate pins. Refer to evaluation platform schematics.
VI2C
D22
Digital supply input
VIO V1OUT V2OUT V2XOUT V4OUT
B20 N15 M12 B14 M16
Supply input (1.8 V) Regulator output Regulator output Regulator output Regulator output
V4_OUTSEL FB_V2 FB_V2X
G24 M11 C14
1.8 V digital input Regulator sense Regulator sense
-
EMU_CREF
J23
Analog reference
-
IRES
J24
Analog reference
VDDA
A1, A2, A3, A8, A11, H2, N7, N12
Analog supply input
-
VDDA_SYNTH K1 VDDS_PRESR K3 VCC_LNA HB_VPA LB_VBA VDDA_PLL B13 M15 N17 M13 3.0 V digital output 3.0 V digital output Analog supply input High Band PA Enable Low Band PA Enable Phase Locked Loop supply = 1.8V
9/40
Pin descriptions Table 1.
Pin name
STLC4420A
STLC4420A signal descriptions (continued)
Pin number Type Internal resistor Function Analog 1.8V supply input for RF Quadrature Local Oscillator (QLO). Decouple to a solid ground plane using a ceramic capacitor located as close as possible to the pin. Refer to evaluation platform schematics. Analog 1.8V supply input for the RF Voltage Controlled Oscillator (VCO). Typically connected to V1OUT pin N15. Decouple to a solid ground plane using a ceramic capacitor located as close as possible to the pin. Refer to evaluation platform schematics. Analog supply input for BIAS control ciruits. Typically connected to V4OUT pin M16. Decouple to a solid ground plane using a ceramic capacitor located as close as possible to the pin. Refer to evaluation platform schematics. Digital 1.8V I/O power supply input pins. Decouple to a solid ground plane using ceramic capacitors located as close a possible to the appropriate pins. Refer to evaluation platform schematics.
VDD_QLO
A4
Analog supply input
-
VDD_VCO
A6
Analog supply input
-
VDD_BIAS
N3
Analog supply input
-
VDDD
B15, J22, M21, N18, E14, E15, L13, N9,G16 B1-B8,B11, C4-C13, D3, E3, F3, F6F11, G6-G11, H6H11, J3, L8L12, M3, N5, N6, N8, N11 G1, G2, G3, H3, J2, K2
Digital supply input
-
AGND
Analog ground
-
All AGND pins must be connected together through a solid ground plane. For optimal performance, refer to the evaluation platform layout for the proper AGND and DGND grounding scheme.
TX_GND
Analog ground
-
All TX_GND pins must be connected together through a solid ground plane. For optimal performance, refer to the evaluation platform layout for the proper grounding scheme. Digital 1.2V core supply. Decouple to a solid ground plane using ceramic capacitors located as close a possible to the appropriate pins. Refer to evaluation platform schematics.
VDD_CORE
A23, B21, C19, E16, M17, M19, N21
Digital supply input
-
DGND
A17,L14, L15, L16, M9, K15, J15, H15, H19, G19, F14, F15, Digital ground F19, F22, E22, C22, E23, N24, B24, A24
-
All DGND pins must be connected together through a common solid ground plane. For maximum performance, refer to the evaluation platform layout for the proper AGND and DGND grounding scheme.
10/40
STLC4420A Table 1.
Pin name EMU_GND EMU_DGND GNDA_PLL
Pin descriptions STLC4420A signal descriptions (continued)
Pin number G15 F16 J16 Type Ground Digital Ground Internal resistor Function Ground of the EMU. Ground of the EMU level shifter.
Miscellaneous Pins GPIO8 G22 1.8V (VDDD) GPIO No Pull Firmware controlled 1.8V digital GPIO Assigned to ARM MAC GP2-11. Float for proper operation. Firmware controlled 1.8V digital GPIO. Assigned to ARM MAC GP2-1. Can optionally be used as a serial data line (SDA) for external 1.8V serial FLASH device. Firmware controlled 1.8V digital GPIO. Assigned to ARM MAC GP2-0. Can optionally be used as a serial clock line (SCL) for external 1.8V serial FLASH device. Firmware controlled 1.8V digital GPIO. Assigned to ARM MAC GP1-13. (Radio_PE). Float for proper operation. Firmware controlled 1.8V digital GPIO -- float for proper operation. Assigned to ARM MAC GP1-15. (FAAmode_n) Firmware controlled 1.8V digital GPIO -- float for proper operation. Assigned to ARM MAC GP2-2. (LED2/TR_SW_Bar) Firmware controlled 1.8V digital GPIO -- float for proper operation. Assigned to ARM MAC GP2-15 (FAA_HDRn). Firmware controlled 1.8V digital GPIO Assigned to ARM MAC GP1-3. Float for proper operation. Firmware controlled 1.8V digital GPIO Assigned to ARM MAC GP1-7. Float for proper operation. Firmware controlled 1.8V digital GPIO Assigned to ARM MAC GP2-13. Float for proper operation. Firmware controlled 1.8V digital GPIO Assigned to ARM MAC GP2-12. Float for proper operation.
GPIO7
L22
1.8V (VDDD) GPIO
No Pull
GPIO6
M23
1.8V (VIO) GPIO
40uA Pull-Down
GPIO5
D15
1.8V (VIO) GPIO
Pull-Up
GPIO4
B18
1.8V (VIO) GPIO
Pull-Up
GPIO3
L24
1.8V (VDDD) GPIO
40uA Pull-Down
GPIO1
L23
1.8V (VDDD) GPIO
No Pull
GP1_3
M22
1.8V (VDDD) GPIO 1.8V (VDDD) GPIO 1.8V (VDDD) GPIO 1.8V (VDDD) GPIO
No Pull
GP1_7
K23
No Pull
GP2_13
H22
No Pull
GP2_12
C16
No Pull
11/40
Pin descriptions Table 1.
Pin name
STLC4420A
STLC4420A signal descriptions (continued)
Pin number Type 1.8V (VDDD) GPIO 1.8V (VDDD) GPIO 1.8V (VDDD) GPIO 1.8V (VDDD) GPIO Internal resistor No Pull Function Firmware controlled 1.8V digital GPIO Assigned to ARM MAC GP2-10. Float for proper operation. Firmware controlled 1.8V digital GPIO Assigned to ARM MAC GP2-9. Float for proper operation. Firmware controlled 1.8V digital GPIO Assigned to ARM MAC GP1-4. Float for proper operation. Firmware controlled 1.8V digital GPIO Assigned to ARM MAC GP2-8. Float for proper operation.
GP2_10
C17
GP2_9
C18
No Pull
GP1_4
C23
No Pull
GP2_8 I_TESTI_TEST+ Q_TESTQ_TEST+
A22 B9 A9
No Pull -
Reserved B10 A10 -
Reserved analog test pins -- float for proper operation.
VCO_CAP
A7
Miscellaneous
-
RF VCO core decoupling pin. Decouple this pin through a ceramic capacitor to VDD_VCO pin A6. Refer to evaluation platform schematics for optimal capacitor value. VCO loop filter pin. Connect this pin to thru a loop filter network to VDD_VCO pin A6. Refer to evaluation platform schematics for optimal filter network. Optional EMU programming I2C clock Optional EMU programming I2C data/address
VCO_LOOP
A5
Miscellaneous
-
EMU_SCL EMU_SDA RSRV_GND
D23 C24 K24
Miscellaneous Miscellaneous Reserved -
Reserved pin. Connect to ground plane for proper operation.
RSRV_NC
D14, D16, G14, H14, H16, J14, K16, L1, L2, L4, L5, L7, Reserved M4, M8, M10, N19, N23, F23, L21, L19, K14 L20 K22 H24 N20 N22 JTAG JTAG JTAG JTAG JTAG
-
Reserved pins. Float for proper operation.
TCLK TDI TDO TMS TRSTN
Pull-Up No-Pull No-Pull Pull-Up Pull-Up
JTAG clock JTAG data input JTAG data output JTAG test mode select JTAG reset
12/40
STLC4420A Table 1.
Pin name
Pin descriptions STLC4420A signal descriptions (continued)
Pin number Type 1.8V (VDDD) digital input 1.8V (VDDD) digital output Internal resistor Pull-Down No-Pull UART serial input UART serial output Function
UART_SIN UART_SOUT
A21 C20
13/40
Electrical specifications
STLC4420A
3
Note:
Electrical specifications
The STLC4420 has an ESD classification of Class TBD.
Warning:
Stresses above those listed in the "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
Table 2.
General electrical specifications
Parameter Test condition / comment Min. Typ. Max. Units
Absolute maximum ratings PMU VBATT (Vcc) Voltage on any other pin Within shared voltage rails Vcc to Vcc decouple Any GND to GND Operating conditions and input power specifications Operating temperature range Input supply voltage Average continuous tx current Average continue rx current Average standby mode current Input supply voltage VDIG supply Input supply current Power Management Unit VBATT supply input Continuous Transmitting @ 54Mbps, VBATT = 3.6 V Receiving Valid Packets @ 54Mbps, VBATT = 3.6 V VBATT = 3.6 V Power management unit VDIG supply for digital buffers VDIG = 3.6 V, Typical load is application dependent VIO input supply determines Host CMOS logic levels for: SPI_CSX, SPI_CLK, SPI_DIN, SPI_DOUT, HOST_IRQ, SLEEP_CLK, FREQ, RF_ACTIVE, STATUS, TX_CONF, GPIO4, GPIO5, GPIO6 VIO = 1.8 V 3 -30 3.0 3.6 TBD TBD 85 3.6 VBATT 85 5.5
oC
-0.3 -0.3 -0.3 -0.3
-
7.0 Vcc + 0.3 +0.3 +0.3
V V V V
V mA mA A V mA
VBATT supply
VIO supply
Input supply voltage
1.62
1.8
1.98
V
Input supply current
-
-
10
mA
14/40
STLC4420A Table 2. General electrical specifications (continued)
Parameter Test condition / comment Min.
Electrical specifications
Typ.
Max.
Units
Internal power management unit (PMU) specifications PMU_CREF PMU_RSET Output Voltage V1OUT Linear Regulator Peak Output Current External Output Load Capacitor Output Voltage V2OUT Linear Regulator Peak Output Current External Output Load Capacitor Output Voltage V2XOUT Linear Regulator Peak Output Current External Output Load Capacitor PMU reference capacitor PMU reference resistor Active Mode Low Power Mode Active Mode Low Power Mode Typical ESR = 0.1 ohm Active Mode Low Power Mode Active Mode Low Power Mode Typical ESR = 0.1 ohm Active Mode Low Power Mode Active Mode Low Power Mode Typical ESR = 0.1 ohm Active Mode: V4_OUTSEL=0 V4_OUTSEL=1 Output Voltage V4OUT Linear Regulator Peak Output Current External Output Load Capacitor Low Power Mode: V4_OUTSEL=0 V4_OUTSEL=1 Active Mode Low Power Mode Typical ESR = 0.1 ohm -35% 1 2.726 3.016 2.81 3.11 2.894 3.203 30 5 +35% mA uF -35% 2.2 -35% 1.159 1.150 2.2 1.2 1.2 -35% 1.759 1.74 1 1.8 1.8 -30% -1% 1.757 1.759 1 1 1.8 1.8 +30% +1% 1.841 1.847 50 5 +35% 1.844 1.860 300 5 +35% 1.244 1.250 280 20 +35% uF M V mA uF V mA uF V mA uF
2.726 3.016
2.81 3.11
2.894 3.203 V
Receiver specifications 802.11b/g (802.11a TBC) RX RF Frequency Range RX LO Frequency Range RF Input VSWR RX LO Phaser Jitter Differential, 100 Ohms reference 50KHz to 10MHz, RMS LO/2 802.11 b/g 802.11 a 2300 4900 4600 2:1 1.25 Deg 2500 MHz 5850 5000 MHz
15/40
Electrical specifications Table 2. General electrical specifications (continued)
Parameter Test condition / comment At LO/2 Frequency. RF front end properly matched and isolated At LO Frequency. RF front end properly matched and isolated b/g Band only. RF front end properly matched CCK CH6 OFDM 54Mbits Ch6 During transmit mode, affecting TX distortion High Gain RX Mode, -90dBm input, b and g Band only, front end losses not included Low Gain RX Mode, -20dBm input, b and g Band only, front end losses not included b/g Band only. RF front end properly matched. 6Mbps OFDM, 10% PER 9Mbps OFDM, 10% PER 12Mbps OFDM, 10% PER 18Mbps OFDM, 10% PER 24Mbps OFDM, 10% PER Receive Sensitivity, b and g band, front end losses not included 36Mbps OFDM, 10% PER 48Mbps OFDM, 10% PER 54Mbps OFDM, 10% PER 1Mbps BPSK, 8% PER 2Mbps QPSK, 8% PER 5.5Mbps CCK, 8% PER 11Mbps CCK, 8% PER -82 -68 -89 -85 -23 35 -1 -10 37 11 +5 5 -17 -16 +13 29.8 +9 +33 -38 -90 -88 -87 -84 -80 -76 -73 -71 -96 -91 -90 -86 7 Min. Typ.
STLC4420A
Max. -70 -50
Units dBm dBm dBm
LO to LNA Input Feed through
Maximum RX input Level Adjacent ChannelRejection TX to RX Input Leakage DSB NF IP3 Input IP2 Input DSB NF IP3 Input IP2 Input RF Hi/Lo Gain Switching Point
dBm dB dBm dBm dB dBm dBm dBm dBm dBm dBm dBm dBm dBm dBm dBm dBm dBm dBm dBm
16/40
STLC4420A Table 2. General electrical specifications (continued)
Parameter Test condition / comment 6Mbps, 10% PER 9Mbps, 10% PER 12Mbps, 10% PER 18Mbps, 10% PER 24Mbps, 10% PER Multipath Delay Spread 36Mbps, 10% PER 48Mbps,10% PER 54Mbps, 10% PER 1Mbps BPSK and 2Mbps QPSK, 8% PER 5.5 and 11Mbps CCK, 8% PER Transmitter specifications 802.11b/g (802.11a TBC) TX RF Frequency Range TX LO Frequency Range RF Output VSWR TX LO Phase Jitter TX AGC Control Dynamic Range TX AGC Control Step Size CCK Output Power CCK Output Power OFDM Output Power Monotonic At 0 control attenuation. RF front end properly matched Case 1: Set TX AGC to obtain this Pout. 5 Note: Over AGC range, b and g Bands only 50KHz to 10MHz, RMS, LO/2 40 802.11 b/g 802.11 a 2300 4900 4600 Min.
Electrical specifications
Typ. 820 430 630 405 320 210 160 120 250 100
Max.
Units ns ns ns ns ns ns ns ns ns ns
2500 MHz 5850 5000 2:1 1.25 Deg dB 2 8 3 -6 -135 dBm dBm dBm dBm dBm/Hz dBm/Hz dBm dBm -137.5 dBm/Hz dBm/Hz MHz
Output Noise Floor
Carrier offsets 0 to 10MHz Carrier offsets >20MHz Case 2: Set TX AGC to obtain this Pout -7 -16
-138
CCK Output Power OFDM Output Power
Output Noise Floor
Carrier offsets 0 to 10MHz Carrier offsets >20MHz
-140.5
17/40
Electrical specifications Table 2. General electrical specifications (continued)
Parameter CCK Output Power OFDM Output Power Test condition / comment Case 3: Set TX AGC to obtain this Pout Min. Typ. -17 -26
STLC4420A
Max.
Units dBm dBm
-140 Output Noise Floor Carrier offsets 0 to 10MHz Carrier offsets >20MHz Case 4: Set TX AGC to obtain this Pout -27 -36 -142.5 Output Noise Floor Carrier offsets 0 to 10 MHz Carrier offsets >20 MHz Case 5: Set TX AGC to obtain this Pout -37 -46 -145 Output noise floor Carrier offsets 0 to 10 MHz Carrier offsets >20 MHz -148 -145.5 -143
dBm/Hz dBm/Hz dBm dBm dBm/Hz dBm/Hz dBm dBm dBm/Hz dBm/Hz
CCK Output Power OFDM Output Power
CCK Output Power OFDM output power
External power amplifier detector ADC specifications Full scale input voltage Maximum input voltage Input resistance Input capacitance External power amplifier BIAS DAC specifications At voltage output compliance > 1.8 V At voltage output compliance = 1.8 V At -40C, full scale output current < 2.5mA, VDD_BIAS = 3.15 V Output voltage compliance Note: An external resistor at PA_RREF pin determines the full scale output current. At +25C, full scale output current < 2.5mA, VDD_BIAS = 3.15 V At +100C, full scale output current < 2.5mA, VDD_BIAS = 3.15 V Full temperature range, scale output current <= 5mA, VDD_BIAS = 3.15 V 2.5 5 mA mA At input of ADC 0 1.0 VDDA At PA_DETx input -- 16 tap resistive divider tap node 30K 0.5 V V Ohm pF
Full scale output current
2.85
V
2.75
V
2.55
V
1.8
V
18/40
STLC4420A Table 2. General electrical specifications (continued)
Parameter BIAS DAC supply voltage Tdod Tdozh SPI_DOUT delay from transmit edge of SPI_CLK SPI_DOUT delay before HI-Z state from rising edge of SPI_CSX SPI_DOUT delay before driven from HI-Z state on falling edge of SPI_CSX Test condition / comment Min. 2.8 0 0
Electrical specifications
Typ.
Max. 3.15 7
Units V ns ns
SPI_DOUT
Tdozd
10
ns
Table 3.
Host interface specifications
Parameter Test condition / comment Min. Typ. Max. Units
Digital interface specifications VIH POWER_UP Input VIL Pull-Down Host CMOS Inputs VIH VIO supply domain VIL VOH Host CMOS Outputs VOL Input Current OSC_EN Input REF_CLK Input VOH VOL Input Level AC coupled Accuracy Frequency SLEEP_CLK Input Accuracy Duty Cycle SPI timing specifications (refer to Figure 3) Tcmin SPI_CLK Tch Tcl Tcssu SPI_CSX Tcsh SPI_CSX hold time from last clock edge 10.4 ns SPI_CLK Period SPI_CLK High Time SPI_CLK Low Time SPI_CSX Setup time to first clock edge 20.8 10.4 10.4 10.4 ns ns ns ns VIO supply domain 30 32.768 25 150 70 ppm kHz ppm % IOH = 0.2mA, VIO supply domain IOL = 6mA, VIO supply domain VIO supply domain IOH <= 2mA IOL <= 2mA 0 VIO - 0.2 0 -1.0 1.4 500 0.3*VIO VIO 0.6 +1.0 0.4 1000 V V V A V V mVpp PMU Power up control. Active High. 0.8 0 0.7*VIO 500 VBATT 0.3 VIO + 0.3 V V K ohms V
19/40
Electrical specifications Table 3. Host interface specifications
Tdisu SPI_DIN Tdih SPI_DIN hold time to receive edge of SPI_CLK 0 SPI_DIN setup time to receive edge of SPI_CLK 3
STLC4420A
ns ns
Figure 3.
SPI timing specification
20/40
STLC4420A
Serial host interface
4
4.1
Serial host interface
Host pins
The Serial Host Interface consists of the following pins:

SPI_CLK: serial host clock input, 0 to 48 MHz. SPI_DIN: serial host data input, sampled on active edge of SPI_CLK. SPI_DOUT: serial host data output, driven when asserted low and floating when deasserted. SPI_DOUT is driven on inactive edge of SPI_CLK. SPI_CSX: serial host chip select, active low chip select. HOST_IRQ: serial host interrupt, active high interrupt to Host.
The serial host interface has 12 modes of operation controlled by 4 variables. The default 4-Wire mode may be changed by a SPI host write to the device status/ control register. If the host requires a different SPI mode for normal operation, the host may need to toggle the necessary SPI pins using GPIO-style interfacing to perform a 4-Wire write sequence to change the mode. The default 4-Wire single word write is show below in Figure 4. Figure 4. 4-Wire mode single word write
The default 4-Wire single word read is shown below in Figure 5. Figure 5. 4-Wire mode single word read
21/40
Serial host interface
STLC4420A
4.2
SPI mode selection
As shown in Table 4, the 12 modes of operation are controlled by 4 variables in the device status/control register. Table 4. Serial host modes of operation
Phase Shift 0 0 1 1 0 0 1 1 0 0 1 1 3-Wire-Mode 0 0 0 0 1 1 1 1 1 1 1 1 3-Wire-Adr DataWait X X X X 0 0 0 0 1 1 1 1 4-Wire 4-WireInv 4WShft 4-WireInvShft 3-Wire 3-WireInv 3-WireShft 3-WireInvShft 3-WireWait1 3-WireInvWait1 3-WireShftWait1 3-WireInvShftWait1 Name Invert Clock 0 1 0 1 0 1 0 1 0 1 0 1
When Invert Clock = 0, SPI_CLK receive edge is the rising edge and SPI_CLK transmit edge is the falling edge. The SPI_CLK polarity can be reversed by a host write to device status/control register to change the Invert Clock = 1. In this case, the SPI_CLK transmit edge becomes the rising edge and SPI_CLK receive edge becomes the falling edge. Figure 6. Single Word Read 4-WireInvMode
Figure 7.
Single Word Read 4-WireShftMode
22/40
STLC4420A Figure 8. Single Word Read 4-WireInvShftMode
Serial host interface
Figure 9.
3-Wire
Figure 10. 3-WireInv
Figure 11. 3-WireShft
Figure 12. 3-WireInvShft
Figure 13. 3-WireWait1
23/40
Serial host interface
STLC4420A
Figure 14. 3-WireInvWait1
Figure 15. 3-WireShiftWait1
Figure 16. 3-WireInvShftWait1
4.3
AHB masters
The DMA engines are contained within the Serial Host interface. The DMA engines access data on the device via a pair of AHB masters. AHB1 is connected to the standard AHB bus which is shared with the CPU and DMA controller AHB masters. The Serial Host has a second AHB master connected to the AHB Ram directly via a AHB2. The Serial Host AHB2 master and the AHB Ram AHB2 slave are the only master and slave on the AHB2 bus. This guarantees sufficient bandwidth for the serial host interface. When the AHB master is accessing APB registers the ApbAccess bit must be set to force the master to use word (32-bit) transfers so that the APB registers are not set to an indeterminate state by a pair of half-word (16-bit) transfers. DMA read data is prefetched when the DMA Read Address is written and the DMA Write Enable is asserted. The host must not read DMA Data register before the prefetch completes. There must be 20 ABClock cycles between the end the Data Phase when DMA Read Address is written and the end of Address Phase which selects the DMA Read register.
24/40
STLC4420A Figure 17. AHB bus timing
Serial host interface
The read data is registered on the 15 SPI_CLK of the address phase. SPI_CSX high time must be 20ABClocks - 15SPI_CLKs. If ABClock period is 100ns (10 MHz) and SPI_CLK period is 40ns then the time between writing DMA write address register and reading the DMA data register is (20 * 100) - (15 * 40) = 1.4us. If the ABClock period is 25ns (40 MHz) then SPI_CSX high time is < 0 for Read data to be valid. In this case, only the Min High time for SPI_CSX must be observed.
4.4
Host registers
The Host can access the registers listed in Table 5. Table 5.
Domain SPI_CLK ARM ARM SPI_CLK SPI_CLK Shared Shared Host Host Shared
Host registers
A14-A8 X00 0000 X00 0010 X00 0100 X00 0110 X00 1000 X00 1010 X00 1100 X00 1110 X01 0000 X01 0010 X01 0100 X01 0110 X01 1000 X01 1010 X10 0100 X10 0110 X10 1000 X10 1100 Access RW R R RW W RW RW RW RW RW Sleep access RW --RW ---RW --Description ARM interrupt ARM interrupt enable Host interrupt Host interrupt enable Host interrupt acknowledge GP1 communication GP2 communication Device control/ status DMA data DMA write control
(1), (2) (1)
Notes
(1), (2)
25/40
Serial host interface Table 5.
Domain Shared Shared Shared Shared Shared
STLC4420A Host registers (continued)
A14-A8 X10 1110 X11 0000 X11 0010 X11 0100 X11 0110 X11 1000 X11 1010 Access RW RW RW RW RW Sleep access -----Description DMA write length DMA write base DMA read control DMA read length DMA read base Notes
1. Readable during Sleep Mode without generating Sleep interrupt. All registers are readable during Sleep Mode. Reading registers not marked as Readable during Sleep will set the ArmAsleep bit in the Host and ARM Interrupt registers. 2. Writable during Sleep Mode. All registers are writable during Sleep mode. Writing registers not marked as writable during Sleep mode requires several 32 kHz clock cycles to complete the write access and will set the ArmAsleep bit in the Host and Arm Interrupt.
The Host accesses each register as a 16-bit register. Registers which are physically 32-bits have 2 addresses in the Host address space. The even address (A9 == 0) is the low 16-bits and the odd address (A9 == 1) is the high 16-bits. A15 is the read bit. A15 is set for reads and cleared for Writes. For example, to write ARM Interrupt[31:16] address bits 15:0 are set to 16'h0100. Address bits 15:0 are set to 16'h8100 to read ARM Interrupt[31:16]. A7 - A0 are don't care bits and can be set to any value by the Host. It is required that a full 16-bit address be sent. The initial data phase does not begin until the 16-bit address phase has completed.
4.5
Host writes
The Host writes to a 16-bit register by sending a 16 bit Address phase with A15 set to zero. The Address phase is followed by a 16-bit data phase. D15 is the first bit of data phase and D0 is the last bit of the data phase. D15 - D0 are written to the selected register on the active edge of SPI_CLK when D0 is present on SPI_DIN. When the register is in the ARM or Shared clock domain the write process begins when on the active edge of SPI_CLK when D0 is present on SPI_DIN. The write completes after the data is synchronized into the ABClock domain. This process takes 3 ABClock cycles. ABClocks are 30us each in Sleep mode! Host must ensure 90us delays between writes to non-Sleep accessible registers when device is in Sleep mode. If less than 16 bits are written during the data phase the data is not written to the addressed register. The SPI_CLK may stop at any time. The current phase (address or data) is not interrupted by a stopped (or slowed) SPI_CLK. The logic remains in the current phase until SPI_CLK resumes or SPI_CSX is de-asserted.
26/40
STLC4420A
Serial host interface
4.6
Host multi-word writes
The Host may write to multiple consecutive 16-bit registers by keeping SPI_CSX asserted and continuing to toggle SPI_CLK after the initial 16-bit data phase has completed. The register address is incremented by 2 at the end of each data phase for all register address except the DMA data register.
Figure 18. Serial host multi-word write
Consecutive writes to the DMA data register are written to the DMA data register with no address increment. Figure 19. Serial host multi-word write DMA data
4.7
Host reads
The Host reads from a 16-bit register by sending a 16 bit Address phase with A15 set to one. The Address phase is followed by a 16-bit data phase. D15 is the first bit of data phase and D0 is the last bit of the data phase. Data is available on SPI_DOUT. Any register may be accessed during Sleep mode. However, the usual synchronization mechanism for ARM or Shared clock domain registers is bypassed in Sleep mode. Read data is unpredictable if the ARM writes to the ARM or Shared clock domain register during a Sleep Mode read by the Host. The SPI_CLK may stop at any time. The current phase (address or data) is not interrupted by a stopped (or slowed) SPI_CLK. The logic remains in the current phase until SPI_CLK resumes or SPI_CSX is de-asserted. If less than 16-bits are read by the host during a data phase to any register except the DMA Data register there is no effect on the internal state of the registers. If less than 16-bits are read by the host during a data phase to the DMA Data
27/40
Serial host interface
STLC4420A
register the contents of subsequent DMA read accesses are unpredictable until the DMA is disabled and restarted.
4.8
Host multi-word reads
The Host may read from multiple consecutive 16-bit registers by keeping SPI_CSX asserted and continuing to toggle SPI_CLK after the initial 16-bit data phase has completed. The register address is incremented by 2 at the end of each data phase for all register address except the DMA data register.
Figure 20. Serial host multi-word read
Consecutive reads from the DMA data register are read from the DMA data register with no address increment. Figure 21. Serial host multi-word read DMA data
28/40
STLC4420A
Serial host interface
4.9
ARM AHB slave access
The ARM accesses the registers of the Serial Host via the AHB slave interface. lists the registers that are implemented. Host only registers are listed for convenience only. Table 6. ARM register
ARM Offset 0x00 0x04 0x08 0x10 0x18 0X20 0x24 0x40 0x44 0x48 0x50 0x54 0x58 R W RW RW R RW RW RW RW RW RW RW RW Access Description ARM Interrupt [31:0] ARM Interrupt Acknowledge [31:0] ARM Interrupt Enable [31:0] Host Interrupt [31:0] Host Interrupt Enable [31:0] Host Interrupt Acknowledge [31:0] GP1 Communication [31:0] GP2 Communication [31:0] Device Control/Status [31:0] DMA Data DMA Write Control DMA Write Length DMA Write Base DMA Read Control DMA Read Length DMA Read Base ARMInt ARMIntAck ARMIntEn HostInt HostIntEn -GP1Com GP2Com --DMAWriteControl DMAWriteLength DMAWriteBase DMAReadControl DMAReadLength DMAReadBase Register Reference
29/40
Registers description
STLC4420A
5
5.1
Registers description
ARM interrupt register
The HOSTMSG bits of this register are written by the Host and generate interrupts to the ARM processor when the corresponding bit is set in the ARM Interrupt Enable register. Writing a logic 1 causes the corresponding interrupt bit to be set. All other bits are unaffected; previously set bits will remain set. This register can be read/written while the device is in sleep Mode (i.e. running off the low frequency oscillator) and not generate an ARM_asleep interrupt.
Note:
Both the ARM and Host Interrupt Register have the bit "ARM_ASLEEP". Although only the host generates this bit it is used as an interrupt source to both. When the Host sees this interrupt, it is expected that it will poll the device control/status Register until the SleepMode status bit is de-asserted by ARM before continuing. The format of the register is defined in Table 7. Table 7. ARM interrupt register
Name ARM_ASLEEP DMA wr done DMA rd done DMA rd ready Reserved HOSTMSG Description Indicates that an access to hardware registers or device memory (by Host) was attempted while the device was in sleep-mode. Last Write Occurred Last Read Occurred DMA rd FIFO ready to be read Not Implemented General purpose Host Message Interrupts. May be written by the Host to cause an interrupt to the ARM Processor.
Bit position 31 30 29 28 27:16 15:0
5.2
ARM interrupt acknowledge
This register is written by the ARM processor and clears bits in the ARM interrupt register. Writing a logic 1 in any bit position causes the corresponding interrupt bit to be cleared. All other bits are unaffected. The format of the register is defined in Table 8. Table 8. ARM interrupt acknowledge
Name ARM_ASLEEP DMA wr done DMA rd done DMA rd ready Description Indicates that an access to hardware registers or device memory (by Host) was attempted while the device was in sleep-mode. Last Write Occurred Last Read Occurred DMA rd FIFO ready to be read
Bit position 31 30 29 28
30/40
STLC4420A Table 8. ARM interrupt acknowledge (continued)
Name Reserved HOSTMSG Not Implemented Description
Registers description
Bit position 27:16 15:0
General purpose Host Message Interrupts. May be written by the Host to cause an interrupt to the ARM processor.
5.3
ARM interrupt enable
The ARM processor writes this register, and enables interrupts from the ARM interrupt register. An interrupt is generated when corresponding bits in both the ARM interrupt register and the ARM interrupt enable register are both logic 1. The format of the register is defined in Table 9. Table 9. ARM interrupt enable
Name ARM_ASLEEP DMA WR done DMA RD done Description Indicates that an access to hardware registers or device memory (by Host) was attempted while the device was in sleep-mode. Last Write Occurred Last Read Occurred
Bit position 31 30 29 28 27:16 15:0
DMA RD ready DMA rd FIFO ready to be read Reserved HOSTMSG Not Implemented General purpose Host Message Interrupts. Written by the ARM to enable Interrupt on selected bit(s)
5.4
Host interrupt register
The bits of this register reflect the Host interrupt register with the masking by the host interrupt enable register. This register can be written or read while the device is in sleep mode (for example, running off the low frequency oscillator) and not generate an ARM_asleep interrupt. The format of the register is defined in Table 10. Table 10. Host interrupt register
Name ARM_ASLEEP DMA wr done DMA rd done DMA rd ready NotSleep Description Indicates that an access to hardware registers or device memory (by Host) was attempted while the device was in sleep-mode. Last Write Occurred Last Read Occurred DMA rd FIFO ready to be read Not Implemented
Bit position 31 30 29 28 27
31/40
Registers description Table 10. Host interrupt register
Name Reserved ARMMSG Not Implemented Description
STLC4420A
Bit position 26:16 15:0
General purpose Host Message Interrupts. Written by the ARM to enable Interrupt on selected bit(s)
5.5
Host interrupt enable register
The Host writes this 32-bit register to enable interrupts from the host interrupt register. A Host interrupt is generated if the corresponding bit in both the host interrupt register and the host interrupt enable register are both active. The format of the register is defined in Table 11. Table 11. Host interrupt enable register
Name ARM_ASLEEP DMA wr done DMA rd done DMA rd ready NotSleep Reserved HOSTMSG Not Implemented General purpose ARM Message Interrupts. Written by the ARM to cause an interrupt to the HOST Description Indicates that an access to hardware registers or device memory (by Host) was attempted while the device was in sleep-mode.
Bit position 31 30 29 28 27 26:16 15:0
5.6
Host interrupt acknowledge register
This 32-bit register is written by the Host, and clears interrupts in the Host Interrupt Register. Writing a logic 1 in any bit position cause the corresponding interrupt bit to be cleared. All other bits are unaffected. The format of the register is defined in Table 12. Table 12. Host interrupt acknowledge register
Name ARM_ASLEEP DMA WR done DMA RD done Description Indicates that an access to hardware registers or device memory (by Host) was attempted while the device was in sleep-mode. Last write occurred Last read occurred
Bit position 31 30 29 28
DMA RD ready DMA RD FIFO ready to be read
32/40
STLC4420A Table 12. Host interrupt acknowledge register
Name Reserved HOSTMSG Not implemented Description
Registers description
Bit position 27:16 15:0
General purpose host message interrupts. Written by the ARM to enable Interrupt on selected bit(s)
5.7
General purpose 1 and 2 communication registers
These 32-bit general-purpose register can be written or read by either the Host or the ARM processor.
5.8
Device control/status register
The device control/status register is used by the Host to configure the device by writing to bits 31:27. The status of the device is visible to the Host by reading bits 22:6. The contents of the register are defined in Table 13. Table 13.
Bit number 31 30 29 28 27 26:23 22 21 20 19
Device control/status register
Name SetHostOverride SetStartHalted SetRAMBoot SetHostReset SetHostCPUEn Reserved StartHalted RestartAsserted Reserved SoftRes Description When set, tells processor to use boot options set by bits 30 and 29 and override boot strapping options after reset. When bit 31 is set, this bit forces CPU to remain idle when reset is de-asserted. (Read/Write) When bit 31 is set, processor boots from RAM. Over-rides TMSEL strapping options (Read/Write) When set, produces an active high(1) reset level to the ARM (Read/Write) Must be cleared to de-assert(0) reset. Enables processor after StartHalted has been asserted. (Read/Write) Not Implemented Indicates that the processor clock was stopped after the previous reset. (Read Only) Indicates that OSC Restart is asserted. (Read Only) Not Implemented Soft Reset flag - A logic 1 indicates that the previous reset was generated by a write to the PMU system control register bit 0. RTC Reset flag - A logic 1 indicates that the previous reset was generated by the Real Time Clock. Hard Reset flag - A logic 1 indicates that the previous reset was generated by asserting the RESET_N pin.
18 17
RTCRes HardRes
33/40
Registers description Table 13.
Bit number 16 HostRes
STLC4420A Device control/status register
Name Description Host Reset flag - A logic 1 indicates that the previous reset was generated by the Host asserting the HostReset bit in this register. SleepMode flag - A logic 1 indicates that the device is in Sleep Mode, i.e. running off the low frequency oscillator. (Read Only) The clock divisor setting on the PMU clock control register (Read Only) Not Implemented When asserted, SerHost mode is updated by bits 3:0 1 = Update SerHost mode based on bits 3:0 0 = No change to SerHost mode Number of wait states between Address and Data phase in 3_Wire mode 0 = Zero wait states between Address and Data phase in 3_Wire mode 1 = One wait state between Address and Data phase in 3_Wire mode Read value is currently selected 3_ WireAdrDataWait. May be different that last written value when UseSerHostOverRide is deasserted. Select 3 wire mode using SPI_DIN for Serial data input and output 0 = Use 4 wire mode, SPI_DIN input only and SPI_DOUT output only 1 = Use 3 wire mode, SPI_DIN for input and output Read value is currently selected 3_ WireMode. May be different that last written value when UseSerHostOverRide is deasserted Shift SPI_DIN and SPI_DOUT by 1 clock phase 0 = No phase shift 1 = Phase shift SPI_DIN and SPI_DOUT by 1 clock phase
15
SleepMode
14:6 5 4
ClockDivisor Reserved UseSerHostOverRide
3
Host_3_WireAdrDataWait
2
Host_3_WireMode
1
Host_PhaseShift Read value is currently selected PhaseShift. May be different that last written value when UseSerHostOverRide is deasserted Select active edge of SPI_CLK 0 = Rising edge of SPI_CLK is active edge 1 = Falling edge of SPI_CLK is active edge
0
Host_InvertClock Read value is currently selected InvertClock. May be different that last written value when UseSerHostOverRide is deasserted
34/40
STLC4420A
Registers description
5.9
DMA data register
The data register allows the Host to read data directly from the RAM, or to write data directly into the RAM. The Read address is post incremented by 2 after each read. The read length is decremented by 2 after each read. Data is prefetched into the DMA data register when the DMA Read Address is written (if the DMA Write Enable bit is set). The Write address is post incremented by 2 after each write. The Write Length is decremented by 2 after each write. It is possible to intermix Reads and Writes to the DMA Data register if the both DMA Read and Write channels are enabled. The format of the register is defined in Table 15. Table 14.
Bit number 15:0 Data
DMA write control register
Name Data DMA Data Register Description
5.10
DMA write control register
The DMA write control register allows the ARM or the Host to enable the DMA write channel. Both ARM and Host are also able to control when 32-bit APB access are utilized. Only the ARM can modify the HostAllowed bit. When the HostAllowed bit is de-asserted the Host is not allowed to write the DMA Write Control, Length or Base registers. Only bits 15:0 are accessible by the Host. The format of the register is defined in Table 15. Table 15.
Bit number 31:8 Reserved When bit is set, the Host is allowed to write to DMA write control, length and base registers. HostAllowed bit is only writable by the ARM. HostAllowed default value is '1'. '0' = Host not Allowed to write Control, Length and Base registers. '1' = Host IS Allowed to write Control, Length and Base registers.
DMA write control register
Name Description
7
HostAllowed
6:4
Reserved Bit must be asserted when DMA is used to write APB registers. '0' = Access is not to APB register '1' = Access is to APB register
3
ApbAccess
2:1 0
Reserved Enable Specifies the access direction
35/40
Registers description
STLC4420A
5.11
DMA write length register
This 16 bit register is programmed with the maximum byte count of the next DMA Write transfer. Only the low-order 16 bits are used. The value programmed can be any number of bytes from 1 to 65535. The format of the register is defined in Table 16. Table 16.
Bit number 31:16 15:0 Reserved Data length Maximum byte count
DMA write length register
Name Description
5.12
DMA write base address register
The DMA Write Base Address is written to point to the first location for the DMA Data register write in the Devices AHB space. The address will be incremented after every Host access to the Data register. There is no restriction on the Base Address. Byte, Half-word, Word and QuadWord addresses are supported. The format of the register is defined in Table 17. Table 17.
Bit number 31:0
DMA write base address register
Name DMA Write Base Description Address for 1st DMA write
5.13
DMA read control register
The DMA Read Control register allows the ARM or the Host to enable the DMA Read channel. Only the ARM can modify the HostAllowed bit. When the HostAllowed bit is deasserted the Host is not allowed to write the DMA Read Control, Length or Base registers. Only bits 15:0 are accessible by the Host. The format of the register is defined in Table 18. Table 18.
Bit number 31:8 Reserved When bit is set, the Host is allowed to write to DMA Read Control, Length and Base registers. HostAllowed bit is only writable by the ARM. HostAllowed default value is '1'. '0' = Host not Allowed to write Control, Length and Base registers. '1' = Host IS Allowed to write Control, Length and Base registers.
DMA read control register
Name Description
7
HostAllowed
6:1 0
Reserved Enable Specifies the access direction
36/40
STLC4420A
Registers description
5.14
DMA read length register
This 16 bit register is programmed with the maximum byte count of the next DMA Read transfer. Only the low-order 16 bits are used. The value programmed can be any number of bytes from 1 to 65535. A value of '0' disables the byte count logic, causing any transfers to continue until terminated by clearing the Enable bit. The format of the register is defined in Table 19. Table 19.
Bit number 31:16 15:0 Reserved Data Length Maximum byte count
DMA read length register
Name Description
5.15
DMA read base address register
The DMA read base address is written to point to the first location for the DMA Data register read in the Devices AHB space. The address will be incremented after every Host access to the Data register. There is no restriction on the Base Address. Byte, Half-word, Word and QuadWord addresses are supported. The format of the register is defined in Table 20. Table 20.
Bit number 31:0
DMA read length register
Name DMA Read Base Description Address for 1st DMA read
37/40
Package information
STLC4420A
6
Package information
Figure 22. LFBGA228 mechanical data and package dimensions
mm DIM. MIN. A A1 A2 A3 A4 b D D1 E E1 e F ddd eee fff 6.85 0.25 12.35 0.30 12.50 11.50 7.00 6.00 0.50 0.50 0.08 0.15 0.05 7.15 0.270 0.15 1.065 0.280 0.800 0.35 12.65 0.010 0.486 0.012 0.492 0.453 0.275 0.236 0.020 0.020 0.003 0.006 0.002 0.281 TYP. MAX. 1.40 0.0059 0.0419 0.0110 0.0315 0.014 0.498 MIN. TYP. MAX. 0.0551 inch
OUTLINE AND MECHANICAL DATA
Body: 12.5 x 7 x 1.4mm
LFBGA228 (207+21) Low Profile Ball Grid Array
7887629 A
38/40
STLC4420A
Revision history
Revision history
Table 21. Revision history
Date 05-Mar-2006 Revision 1 Initial release. Changes
39/40
STLC4420A
Please Read Carefully:
Information in this document is provided solely in connection with ST products. STMicroelectronics NV and its subsidiaries ("ST") reserve the right to make changes, corrections, modifications or improvements, to this document, and the products and services described herein at any time, without notice. All ST products are sold pursuant to ST's terms and conditions of sale. Purchasers are solely responsible for the choice, selection and use of the ST products and services described herein, and ST assumes no liability whatsoever relating to the choice, selection or use of the ST products and services described herein. No license, express or implied, by estoppel or otherwise, to any intellectual property rights is granted under this document. If any part of this document refers to any third party products or services it shall not be deemed a license grant by ST for the use of such third party products or services, or any intellectual property contained therein or considered as a warranty covering the use in any manner whatsoever of such third party products or services or any intellectual property contained therein.
UNLESS OTHERWISE SET FORTH IN ST'S TERMS AND CONDITIONS OF SALE ST DISCLAIMS ANY EXPRESS OR IMPLIED WARRANTY WITH RESPECT TO THE USE AND/OR SALE OF ST PRODUCTS INCLUDING WITHOUT LIMITATION IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE (AND THEIR EQUIVALENTS UNDER THE LAWS OF ANY JURISDICTION), OR INFRINGEMENT OF ANY PATENT, COPYRIGHT OR OTHER INTELLECTUAL PROPERTY RIGHT. UNLESS EXPRESSLY APPROVED IN WRITING BY AN AUTHORIZE REPRESENTATIVE OF ST, ST PRODUCTS ARE NOT DESIGNED, AUTHORIZED OR WARRANTED FOR USE IN MILITARY, AIR CRAFT, SPACE, LIFE SAVING, OR LIFE SUSTAINING APPLICATIONS, NOR IN PRODUCTS OR SYSTEMS, WHERE FAILURE OR MALFUNCTION MAY RESULT IN PERSONAL INJURY, DEATH, OR SEVERE PROPERTY OR ENVIRONMENTAL DAMAGE.
Resale of ST products with provisions different from the statements and/or technical features set forth in this document shall immediately void any warranty granted by ST for the ST product or service described herein and shall not create or extend in any manner whatsoever, any liability of ST.
ST and the ST logo are trademarks or registered trademarks of ST in various countries. Information in this document supersedes and replaces all information previously supplied. The ST logo is a registered trademark of STMicroelectronics. All other names are the property of their respective owners.
(c) 2006 STMicroelectronics - All rights reserved STMicroelectronics group of companies Australia - Belgium - Brazil - Canada - China - Czech Republic - Finland - France - Germany - Hong Kong - India - Israel - Italy - Japan Malaysia - Malta - Morocco - Singapore - Spain - Sweden - Switzerland - United Kingdom - United States of America www.st.com
40/40

▲Up To Search▲

Price & Availability of STLC4420A

	To Download STLC4420A Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .